Europe, meanwhile, has its own set of limits. The European Union's EMC directive, 89/336/EEC, came into effect in 1996. Since then, a new directive (95/54/EEC) aimed specifically at the European auto industry has been introduced. It is to take effect by October 2002. The directive has two emissions-test requirements for equipment that is not in direct control of the vehicle: broadband emissions, or the noise caused by the high-voltage discharge across the contacts of a spark plug, which is used to ignite the fuel in the engine cylinder; and narrowband emissions from the microcontroller electronics units.

To check the vehicle's susceptibility to electromagnetic radiation, the entire vehicle is subjected to a reference level of 24 V/meter rms over 90 percent of the 20- to 1,000-MHz band and 20 V/meter rms over the whole band. The driver's direct control of steering, braking and engine speed is exercised during the test, and no degradation that would cause confusion to anyone else on the road or degradation of the driver's direct control of the vehicle is allowed.

Design for EMC is important for a number of reasons. The continual decrease in chip geometries and increase in clock speeds result in devices emitting appreciable clock harmonics above 500 MHz. An example of this is the latest e500-based MPC5500 family of system-on-chip microcontrollers from Motorola, which are targeted for 200-MHz operation in a 0.1-micron process.

Moreover, cost requirements for today's products are forcing manufacturers to eliminate ground planes and reduce component count on their printed-circuit boards. The vehicular designer is faced with very severe constraints. Electronic systems must be highly reliable, since a single failure in just one of millions of vehicles may not be tolerated. The recall of a fleet of vehicles due to lack of attention to EMC issues might prove exceedingly costly, and affect manufacturer credibility.

The term "victim" is often used to describe the component that suffers because of a lack of EMC. The victim can be internal to the MCU-based pcb or module, or it can be an external system. Typical victims could be wideband receivers in keyless-entry modules in automobiles or garage door opener receivers, where the MCU generates enough noise for the receiver to think it has gotten a remote signal. Automobile radios are often victims-the MCU might generate sufficient harmonics in the FM band to disturb the sound quality. So are other modules distributed throughout the vehicle, where emissions escape from one MCU-based module via a cable harness. Cordless telephones and pagers may also be susceptible, if the MCU generates sufficient noise to disrupt text and voice communications.

Design Considerations
Many techniques used to provide EMC are applicable to both circuit-board and SoC design. The common elements are transmission-line effects, parasitic resistance, capacitance and inductance effects on routing lines and power supply distribution. Of course, SoC design also has many chip-specific techniques to address, related to substrate material, device geometries and packaging.

Let's take transmission-line effects first. If there is an impedance mismatch between the transmitter and receiver, the propagating wave front can be reflected and cause voltage ringing that can reduce noise margins and increase crosstalk and emissions through capacitive coupling. The transmission-line dimensions on the IC are usually too small for radiated-noise emission or reception, but on circuit boards they can be significant. The favored solution there is to use series termination.

In an SoC design, noise is mostly conducted through parasitic resistance and capacitance rather than being radiated as an electromagnetic field. To increase latchup immunity, CMOS chips use an epitaxial process to provide a very low-resistance substrate. The downside is that this also provides an efficient conduction path for substrate noise, which makes it hard to electrically separate a noise source from a susceptible node.

The many parallel p+ substrate contacts provide a very low-impedance path for resistively coupled noise. Capacitively coupled noise occurs because of the parasitic capacitances formed between the side walls and bottom of the n-well and the p-substrate for p-channel transistors, and the pn junction formed between the substrate and source for n-channel transistors (Fig. 1).

While the capacitance of a single pn junction is extremely small, their parallel sum in a VLSI SoC design can reach a few nanofarads. This capacitance can be shorted out by shorting the sources and substrate contact together before connection to the power rail. This technique has the added advantage of eliminating body effects caused by negative transients into the substrate. The body effect causes an increased depletion region, resulting in higher transistor Vts. The same technique can be applied to the p-channel transistors in the n-well to reduce capacitively coupled noise.

However, digital circuits that contain stacked transistors, or analog circuits in general, require isolation of the source. In this case adding Vss-to-substrate or Vdd-to-well capacitance can lower noise transients. Moreover, for analog designs, body effect might seriously degrade performance of the circuit by altering biasing currents and signal bandwidths. Therefore alternative solutions, such as separate wells, need to be used. For digital circuits, a single well is desirable since it reduces chip area. Body effects can be compensated for by careful design.

Depending on the process technology, another source of substrate noise is impact-ionization current. This is generated when an NMOS transistor reaches its pinch-off voltage. Impact ionization causes a hole current (positive transient) in the substrate. In Motorola's process, impact ionization is a secondary effect.

Because substrate noise frequency can exist up to the 1-GHz range, the phenomenon of skin effect may have to be taken into consideration. The skin effect is the condition of increasing inductance with increasing depth through a conductor, reaching a peak at its center. It can cause on-chip signal attenuation and distortion in the p+ substrate layer of the chip. Minimizing the effect would require thinning the substrate to less than 150 microns-much less than the minimum allowable mechanical thickness of some substrates, since thinner substrates would just be too fragile.

Noise Sources
There are four main sources of noise within a microcontroller-the currents on power and ground lines caused by simultaneous switching of internal buses and nodes; output-pin transitions; oscillator operation; and unwanted on-chip signal artifacts caused by switching capacitive loads.

Simultaneous switching noise (SSN) can be alleviated by a number of design methods. For instance, shoot-through currents could be a major source of this type of noise, since all clock drivers, bus drivers and output pad drivers may potentially suffer from this effect. The effect is caused in complementary inverter stages where the p- and n-channel transistors transiently, but simultaneously, conduct during a change of state in the output. Shoot through is minimized by ensuring one transistor is turned off before the complementary one is turned on. In high-current driver designs this might require a pre-driver to control the slew rate at the node.

SSN also can be reduced by providing the capability to shut off the clocks to unused modules. Clearly this technique is highly application dependent, but might make the difference between EMC compliance and noncompliance. In highly integrated microcontrollers such as the Motorola MPC555 and 565, all on-chip peripheral modules have this capability.

SSN also contributes to radiated emissions. The transient power and ground currents flow through the pins of the device to an external decoupling capacitor. If the loop formed by this circuit (which includes the bond wire and package lead frame as well as the pcb trace) are large enough, then radiated emissions may result. Parasitic inductances in these elements may result in voltage drops, which might also contribute to common-mode radiated emissions.

The magnitude of a common-mode radiated field, E, is given by the equation:

E = 1.26 x 10-6 Iw f l/d

where E is in volts/meter, w is current in amps, f is frequency in Hertz, l is length of path and d is distance from the path in meters. Very often frequency is non-negotiable since in state-of-the-art designs, frequency is fixed by the application requirements. So the SoC designer must work to reduce I or l.

SSN may also be reduced by careful attention to clock domains. Most good SoC designs are synchronous, which gives them the opportunity to generate large peak currents on the clock edges. Distributing the clock drivers across the chip, rather than having one large driver, can spread out the transient currents. Another possibility is to consider making the clocks nonoverlapping. Of course, care must be taken to avoid race conditions caused by timing mismatch. Needless to say, the clocks should be physically distant from sensitive I/O logic, especially analog circuitry.

Today's complex embedded MCUs have many output signals, most of which must be capable of rapid response in the face of capacitive loads. These signals include clock, data, address and high-frequency serial communications. As with internal nodes, shoot-through and capacitive loads contribute to noise as a result of output-pin transitions. The same techniques used for dealing with internal nodes are used to solve noise issues on the output-pin driver circuits. Additionally, fast transitions on the pins can result in reflection-induced ringing and crosstalk on the output traces.

A number of solutions exist to minimize this type of noise source. Output drivers can be designed to control the drive strength, and a slew-rate control circuit can be added to limit di/dt. Drive-strength control is generally preferable to a fixed value, since most device testers have a higher test-node capacitance than the final application.

For example, full-drive strength for CLKOUT on the MPC5XX family of MCUs assumes a load of 90 pF and is intended for test purposes only. Unless full-drive strength is required for timing considerations, it is recommended that a reduced drive strength be used.

An important point to note is that while the techniques described will have a positive impact on noise reduction, the average current may in fact rise, because of the elongation of the transient-current profile. Noise generated by large transients on the output pins can also be reduced by implementing an LVDS physical layer on-chip. It relies on a differential-mode current source driving a low-impedance external load (Fig. 2). The voltage swing is limited to around plus/minus 300 mV.

The additional pin count to support this technique may be offset by the possible reduction in power supply pins, due to the reduction in transient on-chip currents that results from this approach. The output driver steers a constant dc current through the power supply, unlike the transient currents that occur with conventional drivers, which produce large voltage swings on capacitive loads.

Two aspects of an oscillator design affect EMC. One is the wave shape of the input and output signals and the other is the ability to dither the frequency to spread the spectrum and reduce its narrowband power.

Being an inherently analog design, oscillators are more sensitive to process, temperature, voltage and loading effects than the digital components in an SoC. These effects mostly can be eliminated by using feedback in the form of an automatic gain control circuit to restrict the amplitude of the oscillator signals. An alternative to AGC is to implement a dual-mode oscillator, which can switch between high- and low-current modes. Initially, at power on, the high-current mode could be used to keep startup time small, followed by switching to low-current mode to minimize noise.

SoC designs that incorporate a phase-locked loop as part of the oscillator circuit can take advantage of frequency dithering to change the clock frequency by minute amounts, so that the fundamental energy is reduced as the frequency is spread over a range of values. Care has to be taken in the overall system design to ensure that the rate of change and range of frequencies do not affect the timing of critical parts of the target application. For example, serial communications such as CAN, asynchronous SCI and timed I/O functions, which prevail in automotive applications, must not be compromised. On-chip switching noise manifests itself as a damped oscillation on the output of the desired signal. It is caused by the combination of an inductance in series with the load capacitance on the chip. For a typical on-chip bus, the load is a long trace connected to a number of tristate buffers. This load is therefore predominantly capacitive, consisting of gate, junction and interconnect capacitances.

The noise can be reduced or removed only by eliminating the inductance or reducing di/dt. It is only a concern if the noise amplitude is sufficient to cause spurious switching of connected nodes.

Reducing susceptibility to external noise sources involves external components as much as internal design considerations. External transients can cause two conditions at the pin. One is an excessive voltage slew rate, which results in capacitively coupled current into the device. The other is a voltage that exceeds the supply rails and ultimately conducts current through resistive paths into the device.

In the auto industry, external RC filters are often used to limit transient-voltage swings and injected current. Care must be take to ensure that the values of external components take into account leakage-current effects, especially on analog inputs.

Bearing in mind that there are often upward of 200 I/O pins on the MCU and peripheral ICs, the extra cost and board space required for this solution means systems engineers are often reluctant to apply it. The best solutions must be implemented on-chip.

Both hardware and software techniques can assist in achieving EMC compliance. For example, many MCUs have a capability to output, on the external bus, internal accesses that would not normally be visible. This facility is sometimes very useful for debugging, but in an inadequately designed system it could cause external bus contention with a corresponding increase in noise.

I came face to face with a similar type of situation some years ago, when I was asked to help resolve a particularly pernicious problem at an automotive-module manufacturer in Europe. The problem was spurious, erroneous reads of the on-chip A/D converter value. It seemed as if noise was interfering with the measurement or conversion in some way. I asked to see the hardware diagram of the system, ostensibly to look at the A/D input components. Everything seemed in order, but I did notice that the external EPROM was decoded in a way that could cause bus contention under very special conditions. The contention in no way affected program execution, but did result in enough noise to occasionally produce a bad A/D result. A quick change in the decode logic fixed the problem, much to the chagrin of the module manufacturer.

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As senior principal staff engineer in Motorola Semiconductor Products Sector's Transportation and Standard Product Group (Austin, Texas), Richard Soja brings 17 years' experience in the automotive market. He holds a BSc degree from Aberdeen University, Scotland.

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